The present inventive concepts relate to a system on chip (SOC) which may reduce dynamic voltage drop.
An application specific integrated circuit (ASIC) technology has developed to an SOC which is a system that includes cores including a chip-set formed of a plurality of chips including a plurality of function blocks. Integrated circuits of the SOC include various function blocks, such as a microprocessor, an interface, a memory array, and a digital signal processor (DSP). The function blocks, which are designed as above and completed to be verified, are referred to as cores.
However, even if it seems that the cores operate normally when they are tested each independently, an additional verification is needed as to whether the plurality of cores are normally connected, after the plurality of cores are manufactured as the SOC. The most effective one among the test technologies that determine an error of logic circuits in the SOC is a scan test method which places flip-flops which are connected by chains in which an identical trigger signal is input at two ends of logic circuits in cores and tests whether each of the logic circuits accurately operates. However, in the scan test method in which changes occur simultaneously in a large number of logic circuits, the dynamic voltage drop may cause a drop of the test reliability of the SOC test. Also, when an error of a path related to asynchronous set/reset signals is tested, the dynamic voltage drop of the SOC, due to output changes of a plurality of flips-flops connected to the asynchronous set/reset signals, may also cause the drop of the test reliability of the SOC test.